1. Field of the Invention
This invention relates to wireless communications systems, and in particular but not exclusively to wireless communications signal receivers suitable for use in direct-sequence spread spectrum systems such as those employing code division multiple access (CDMA) techniques.
2. Description of the Related Art
In a standard CDMA receiver, digital correlation techniques are conventionally employed, involving an analog-to-digital converter (ADC) that operates at typically four times the chip rate. In currently proposed third-generation communication systems that rate may be in the region of 16 MHz. In addition to the ADC, a high-order square-root raised cosine filter is also required on the receiver side to obtain optimal performance. If this filter is implemented by digital means, it would also typically operate at four times the chip rate.
One of the primary applications for CDMA communications systems is in cellular telecommunications, where receiver circuitry is incorporated in a portable handset or the like. In order to extend the battery life for operation of the portable handset, it is desirable to utilize circuitry therein that is as power efficient as possible. It is therefore desirable for the handset circuitry, such as that in the CDMA receiver, to be low in power consumption. One way in which power consumption can be reduced is to reduce the rate of operation of processing components such as analog-to-digital converters and the like.